The switched mode power supply (SMPS) is a well-known type of power converter having a diverse range of applications by virtue of its small size and weight and high efficiency, for example in personal computers and portable electronic devices such as cell phones. An SMPS achieves these advantages by switching one or more switching elements such as power MOSFETs at a high frequency (usually tens to hundreds of kHz), with the frequency or duty cycle of the switching being adjusted using a feedback signal to convert an input voltage to a desired output voltage. An SMPS may take the form of a rectifier (AC-to-DC converter), a DC-to-DC converter, a frequency changer (AC-to-AC) or an inverter (DC-to-AC). Commonly, to minimise power loss in a power distribution system, the power is distributed at high voltage levels and then transformed to the required level near the load using a rectifier or DC-to-DC converter.
FIG. 1 shows a background example of a hard-switched, isolated SMPS, i.e. an SMPS which converts an input voltage Vin to an output voltage Vout whilst isolating the input from the output through an isolation transformer. The SMPS 100 is provided in the form of a full-bridge (DC-to-DC) converter which has on its primary side a primary side drive circuit having transistors Q1, Q2, Q3 and Q4 (which may, for example, be field-effect transistors such as MOSFETs or IGBTs) which are connected between the power supply's inputs and to the primary winding 111 of the isolation transformer 110 in a full-bridge arrangement, as shown. The transistors Q1 to Q4 are thus configured to drive the primary winding 111 in response to switching control signals applied thereto. In high-power applications, higher converter efficiency can often be achieved with the full-bridge primary side topology than with other topologies, such as half-bridge or push-pull.
The switching of the transistors is controlled by a switching control circuit comprising a switch driving circuit 120, a switching controller 130 in the form of a pulse width modulation (PWM) controller, and a feedback signal generator 140. The driving circuit 120 comprises a pulse width modulator which generates respective drive pulses to be applied to the gates of transistors Q1 to Q4 in order to turn the transistors ON or OFF, the drive pulses being generated in accordance with switching control signals provided to the drive circuit 120 by the switching controller 130. In turn, the switching controller 130 is arranged to receive a feedback signal generated by the feedback signal generator 140, which in this example is provided in the form of an error amplifier. The feedback signal generated by the feedback signal generator 140 provides a measure of the difference between the output of the SMPS 100 (here, the output voltage Vout) and a reference for the output, which is a reference voltage Vref in the present example. In the present example, the feedback signal from the feedback signal generator 140 passes through an electrical isolation barrier 150 (e.g. one or more opto-electric converters) provided between the primary and secondary side circuits of the SMPS 100.
FIG. 1 also shows a standard topology on the secondary side of the isolated SMPS 100, which includes a rectifying circuit and an LC filter connected to a load R. The inductor L of the LC filter is connected to the secondary winding 112 of the transformer 110. A centre-tap (or “mid-tap”) 113 is provided between a first portion of the secondary winding 112 having n2 turns and a second portion of the winding 112 also having n2 turns. In the present example, the rectifying network in the secondary side circuit employs two transistors, Q5 and Q6, to yield full-wave rectification of the voltage induced in the secondary winding 112. Each of the switching devices Q5 and Q6 can take any suitable or desirable form, and are preferably field-effect transistors in the form of a MOSFET or an IGBT, for example. In the example of FIG. 1, the switch devices Q5 and Q6 have an internal body drain diode, which is not shown in the switch device symbol in FIG. 1. The switching of these transistors is controlled by the same controller circuit that controls the switching of transistors Q1 to Q4, namely that comprising the drive circuit 120, the switching controller 130 and the feedback signal generator 140. As shown in FIG. 1, the switching control signals for transistors Q5 and Q6 generated by the switching controller 130 also pass through the electrical isolation barrier 150.
The control circuit drives transistors Q1 to Q6 such that the switching of the primary side transistors Q1 to Q4 is synchronized with that of the secondary side transistors Q5 and Q6, as will be explained in the following. It is noted that the switching controller 130 may alternatively be located on the secondary side of the SMPS circuit shown in FIG. 1. In other words, the switching controller 130 and the isolation barrier 150 in FIG. 1 may be interchanged. In that case, the driving circuit may also be located on the secondary side, with the switching control signals for transistors Q1 to Q4 passing through the isolation barrier 150.
The principles of operation of the SMPS shown in FIG. 1 will be familiar to those skilled in the art, such that a detailed explanation thereof is unnecessary here. Nevertheless, some of the features necessary to assist understanding of present invention will now be discussed.
FIG. 2 shows the switching cycle diagram in accordance with which the gate electrodes of switches Q1 to Q6 in FIG. 1 are driven by the SMPS control circuit so that the primary side circuit generates a series of voltage pulses to be applied to the primary winding 111 of the transformer 110. In FIG. 2, “D” represents the duty cycle of the primary side switching and “T” the switching period. The operation of the circuit during the four time periods 0 to DT, DT to T/2, T/2 to (T/2+DT) and (T/2+DT) to T is as follows.
Time period 1 (0<t<DT): Switching devices Q1 and Q4 are switched ON while Q2 and Q3 are OFF, allowing the input source at Vin to drive a current through the primary winding 111 of the transformer 110. During this period, switching device Q5 is switched ON while device Q6 is switched OFF, allowing the source to transfer energy to the load R via the secondary winding 112 of the transformer 110. The output voltage Vout=n2/n1·Vin·D, where n1 is the number of turns in the primary winding.
The operation of the half-bridge isolated buck converter of FIG. 1 is to be contrasted with that of a flyback converter (or a combined forward/flyback converter), where energy is stored in an air gap provided in the transformer core during this period, to be subsequently released into the secondary side circuit when the primary winding of the transformer is not being driven. No such air gap is present in the core of transformer 110 shown in FIG. 1 or in any of the related circuits described in the embodiments.
Time period 2 (DT<t<T/2): Switches Q5 and Q6 are both conducting and the current in the secondary side circuit therefore free-wheels through both portions of the secondary side winding in substantially equal measure, allowing the transformer flux to be balanced. In other words, the free-wheeling current generates two magnetic fluxes within the secondary winding with opposite directions in the vicinity of the centre-tap 113, yielding a net magnetic flux equal to zero in an area between the first and second portions of the secondary winding 112. Hence, the transformer core magnetization is balanced to zero, and the current in the primary winding during the free-wheeling period DT-T/2 is suppressed, thereby avoiding losses in the primary winding. Thus, the transformer volt-second balance is obtained over the switching period T so that a transformer reset is unnecessary.
Time period 3 (T/2<t<T/2+DT): In this interval, switching devices Q1 and Q4 are OFF while devices Q2 and Q3 are switched ON, exciting the primary winding 111 with a voltage of opposite polarity to that in the first time period described above. On the secondary side, switch Q6 remains ON while switch Q5 is turned OFF, allowing the EMF generated in the lower portion of the secondary winding to drive a current through the inductor L.
Time period 4 (T/2+DT<t<T): The operation proceeds as in time period 2 described above.
Before the above-described operation is established, the SMPS 100 is required to start up from an inoperative state, and in some cases against a bias voltage at its output that is provided by the load circuitry connected to the SMPS 100, i.e. to perform a so-called “pre-bias start”. If this bias is not taken into account during start-up, the output will be pulled to a level dictated by the internal reference Vref, which can damage the load circuitry. This can be avoided by setting the reference to a value corresponding to the output voltage, or by delaying the start the SMPS 100 until the reference Vref has reached the correct value. Typical solutions to this problem involve gradual start-up of the switching elements Q5 and Q6 by ramping up the gate voltage to achieve the desired performance. However, if the SMPS 100 performs a pre-bias start with the switching elements being driven according to the timing sequence shown in FIG. 2 from the outset, the magnetisation in the transformer 110 acquires an initial offset, which is manifested in a transient in the output voltage Vout of the SMPS 100.
To address this problem, WO 2009/154545 A1 discloses a pre-bias start-up procedure in which the duration of an initial voltage pulse applied to the primary side circuit is reduced in relation to the pre-determined duration of subsequent pulses, which is set by the switching controller 130 on the basis of a determined (e.g. measured) initial value of Vout. The duration of this initial pulse is preferably 50% of the pre-determined pulse width.
FIG. 3 shows an example of the switch timing sequence of this improved SMPS start-up procedure, which may be used in the SMPS 100 of FIG. 1. As shown in FIG. 3, an initial pulse of duration DT/2 is applied to each of transistors Q2 and Q3 prior to the start of conventional switching at time t=0, which proceeds according to the timings illustrated in FIG. 2. The initial shortened pulse has the effect of balancing the flux in the transformer 110, thereby reducing the initial offset in its magnetisation and the consequent transient in the power supply's output voltage. This initial reduced-length pulse is hereafter referred to as the “transformer flux balancing pulse”. Start-up of the SMPS using the transformer flux balancing pulse has the further advantage of allowing the SMPS 100 to start up quickly, without any gradual ramp-up of the transistor drive voltage. Furthermore, this solution (hereafter referred to as “reduced-pulse transformer balancing”) can be implemented simply by modifying the switching controller 130 and is therefore much simpler and cheaper to implement than known solutions devised in the analog domain, which typically require complex start-up nets to delay the turn-on of the transistors, rapidly charge the reference Vref, or similar.